Incorporated herein is a computer program listing microfiche appendix of source code used to generate parameter values from the behavioral model netlist and to monitor those values on clock edges. Further incorporated herein is a microfiche appendix of a USERS MANUAL which describes graphical user interface (GUI), a data dependency graph (DDG), and an architectural model obtained from GUI and DDG. Copyright, 1993, C.A.E. Plus, Inc. A portion of the disclosure to this patent document contains material which is subject to copyright protection. The copyright owner has no objected to the facsimile reproduction by anyone of the "microfiche appendix", as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
This invention relates to computer-aided synthesis and verification of a digital device and, more particularly,to an object-oriented representation of the digital device, and the conversion of said device from a behavioral level to an register transfer level (RTL) of structural abstraction.
2. Description of the Relevant Art
Computer-aided design is a tool which allows the circuit or systems designer to produce a low level structural description of the circuit and system from a higher level of design abstraction. There are many types of design tools which aid the designer in bringing his design from an idea or concept to a structure which will be eventually embodied within a working circuit or system. Design tools therefore produce cost-effective development of commercial electronics and streamline the design/development process.
In 1981, the U.S. Government initiated an effort to standardize design tools such that the standardized tool would be technology independent and not be tied to a particular simulator or simulator vendor. Accordingly, the standardized tool would be capable of synthesizing and/or verifying various hardware technologies including MOS, bi-polar, ECL, etc., and also would be capable of operation on any and all simulators. The efforts by the U.S. Government culminated in a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language ("VHDL") language. VHDL language is described and set forth as an IEEE standard 1076 (herein incorporated by reference).
To gain understanding of computer-aided design, and the terms related thereto, a basic understanding of VHDL is required. VHDL is a language for describing general digital hardware devices. VHDL language is therefore a standardized tool which includes various levels of design description including: behavioral, timing, and structural. Each description is represented as a model of a discrete hardware element.
In describing the behavioral description model, a basic premise is understood: a digital device is a collection of operations applied to values being passed through the device. In VHDL, each operation is referred to as a process, and the pathways in which values (e.g., one or zero binary value) are passed through the system are referred to as signals. A process is often viewed as a program, and a program is constructed out of procedural statements called subprograms much like a program written in general purpose procedural language like Pascal or C. FIG. 1 illustrates a process in which an operation exclusive ors two input signals to produce an output signal. The VHDL behavioral model is a collection of independent programs or processes running in parallel. In order to coordinate a set of processes running concurrently, a mechanism is defined to handle the communication between process, wherein this mechanism is the signal. In particular, signals define a data pathway between two processes. The data pathway (often referred to as data path) is directed; one side of the pathway generates a value and the other side receives the value. As such, all communication between processes take place over these pathways to form a data path within and between the modeled digital device.
Referring now to FIG. 2, data pathways 12 are shown connecting processes 10. General timing description model is understood by the concept of stimulus-response paradigm. Once a digital device receives a stimulus, the device responds and then waits for another stimulus. Accordingly, when process 10 generates a value on a data pathway it may also designate the amount of time before the value is sent over the pathway, and this is referred to as scheduling a transaction. It is possible to schedule any number of transactions or events (changes in value) for a given pathway 12.
Most designers design at a structural level. A structural description model 14 is shown for a specific digital device which, in the example provided, is a sequential device having two input ports 16 and a singular output port 18. Data flow within model 14 arrives in parallel at the first stage 20 and, based upon the output values produced, provides an output event from the second stage 22. Scheduling of events and placement of values at select data pathways in a timing model is often times difficult to achieve and simulate.
The VHDL designer models structure 14 by performing what is often called an entity declaration. Processes within the structural model can also be coded in a process statement. As an example, the VHDL entity declaration (structural description) of a half adder digital device is as follows:
entity Half.sub.-- adder is PA1 end Half.sub.-- adder; PA1 architecture Behavioral.sub.-- description of Half.sub.-- adder is begin PA1 end Behavioral.sub.-- description;
port ( PA2 X: in Bit; PA2 Y: in Bit; PA2 Sum: out Bit; PA2 Carry: out Bit); PA2 process PA2 end process;
The VHDL process statement (behavioral description) of the exemplary half adder device is as follows:
Sum&lt;=X xor Y after 5 Ns; PA3 Carry&lt;=X and Y after 5 Ns; PA3 wait on X, Y;
VHDL coding comprises behavioral or structural description language, exemplary such language is set forth above. Additionally, VHDL language can include a mixture of behavioral and structural language. In all instances, however, there is no synergism between the behavioral and structural language. In other words, even if both behavioral and structural language are contained within a code listing for a specific device, the designer must manually change the behavioral description for a chosen structural description and vice versa. There is no linkage between operations unless the designer enters (i.e., codes) a linkage. Unfortunately, any change to one model requires manual change to the other. Manual translation between models necessary to ensure consistency and obtain a complete modeling outline is time-consuming. A VHDL user will oftentimes discontinue burdensome manual entry and focus upon only one model (behavioral or structural) rather than continuing translation.
An important aspect of VHDL is the standardized language used to represent or model a digital device at various levels of design description language. The final modeling outcome of VHDL is a structural level of design description termed register transfer level (RTL). RTL is well known in the art as being a description representative of structural aspects of the device. Accordingly, RTL includes a data path comprising numerous physical elements (registers and transfer elements) and a control path which provides control signals to the data path. The data path elements are actuated in timed sequence by the control path comprising a finite state machine (FSM) and control logic such as select, decode and enable elements.
FIG. 3 is provided to gain a further understanding of the distinctions between data path and control path. Data path 34, represents only a portion of the RTL modeled device. The other portion, or control path 36, is used to control values and events placed upon elements or components within data path 34. FIG. 3 illustrates data path 34 as a set of concurrent registers 38 controllable by enable circuits 40. Various other transfer devices, such as tri-state 42 and data bus 50 are shown. Arithmetic logic unit (ALU) 44 provides arithmatic Boolean operations under the timed direction of select devices 56. Each device, whether it is a ALU, register, MUX or tri-state, can be modeled within a larger model to form a hierarchial description of a system down to smaller component devices, and possibly down to the gate level. Data path 34 also may include various latch elements 52, wherein latch 52, registers 38, and tri-state devices 42 are enabled by enable circuit 40 within control path 36. Selection of input ports within each MUX is decoded by decoders 54, and ALU 44 functions are selected by select element 56. Proper timing of events and presentation of values is achieved within finite state machines (FSM) 58, embodied within the control path portion 36. FSM 58 comprises well-known principles of state machines, and includes a finite number of states 60, and transitions 62 of each associated state. State variables define values upon control bus 64 at select times or events. The values and events are transferred to select, enable and/or decode logic, where they are then used to control data flow within data path portion 34. Controlled data is then presented to data path 50 and transferred to other digital devices, not shown.
Current VHDL behavioral model only encompasses data flow within and through a data path. Data flow is directed by a control model which must be manually created and coded into VHDL language by updating, for example, the process statements, an exemplary process statement is shown above. It would be advantageous to provide modeling of both the data flow and control flow in a synergistic model, wherein changes to data flow model cause automatic changes to control flow model and vice versa. It would further be advantageous to represent both data flow and control flow in a behavioral description. A higher level behavioral description alleviates the disadvantage of detailed modeling often necessary in lower level structural descriptions. Thus, behavioral descriptions minimize the time and effort necessary to achieve thorough representation and modeling of the device. Still further, it would be advantageous to translate the behavioral description to a structural RTL description without requiring the user to manually update control parameters whenever data flow components change. It would still be further advantageous to provide a behavioral representation in graphic or object-oriented terminology thereby making initial representation user-friendly by avoiding textual representation associated with VHDL coding. It would be advantageous for the user to enter code using graphical icons, and to achieve a comprehensive RTL model from the icon description.